Procedure

Current Q-SYS products with GPIO (Core Proccessor, IO Frame, IO8-Flex, etc.) provide 3.3-volt TTL output. Some third party devices such as SurgeX power sequencers, though, expect 5-volt TTL signals and might not reliably work with the Q-SYS GPIO. Using a pair of common resistors, it is possible to build out a Q-SYS GPIO output so it will provide 5 to 6-volt logic to the target device.

You will need to build out each GPIO that needs to drive a 5-volt TTL input.

Resistor voltage divider build-out

The build-out comprises two identical resistors, R1 and R2 (see diagram below), arranged to form a voltage divider between the +12 V pin on the GPIO terminal strip and the GND pin. The value of each resistor should be 1 kΩ but may be as low as 470 Ω, as long as they are identical. The GPIO pin must be configured as open-collector, and it connects to the junction between the resistors. When the open-collector GPIO pin is inactive, the voltage at this point is 6 volts; when the pin is active, it pulls the voltage to 0 volts.

Thus, GPIO active = TTL low; GPIO inactive = TTL high.
Configure the logic in your Q-SYS design accordingly; there is a LogicNOT block available to invert logic.

Resistor power calculation

Select resistors R1 and R2 with a suitable power dissipation rating. Calculate your needs using the equation P = E^2 / R, where E = 12 volts and R is the value of each resistor.

If each resistor is 1 kΩ, this works out to 12 × 12 / 1000 = 0.144 W, so commonly available 1/4-watt resistors will suffice.
If each resistor is 470 Ω, the power dissipation will be  12 × 12 / 470 = 0.306 W, so you should select 1/2-watt resistors.